A semiconductor device in which an electrically rewritable non-volatile memory and a microcomputer are embedded on a single silicon substrate has been widely used as an embedded microcomputer for industrial machines, home appliances, in-vehicle devices and the like.
The non-volatile memory of the semiconductor device described above stores therein a program required by the microcomputer and uses it as needed. As a cell structure of such a non-volatile memory suitable for embedding, there is a split-gate memory cell in which a select MOS (Metal Oxide Semiconductor) transistor and a memory MOS transistor are connected in series.
Among the split-gate memory cells, especially, a memory cell structure in which a gate electrode of the memory MOS transistor (hereinafter, referred to as memory gate) is arranged on a sidewall of a gate electrode of the select MOS transistor (hereinafter, referred to as select gate) by using self-alignment technique can reduce the gate length of the memory gate to be equal to or shorter than the minimum resolution of lithography. Therefore, fine memory cells can be realized compared to a memory cell structure in which the select gate and memory gate are independently formed by etching using a photoresist film as a mask (e.g., Japanese Patent Application Laid-Open Publication No. 2003-046002 (Patent Document 1) and “1997 Symposium on VLSI Technology Digest of Technical Papers (1997) pp. 63-64” (Non-Patent Document 1)).
Of the two kinds of MOS transistors which configure the split-gate memory cell, the memory MOS transistor stores information by holding charges in its gate insulating film. This charge-holding method mainly includes two types of methods. One is a floating-gate method in which a conductive polycrystalline silicon film isolated electrically is used for a part of the gate insulating film (e.g., Japanese Patent Application Laid-Open Publication No. 2004-363122 (Patent Document 2) and “2000 Symposium on VLSI Technology Digest of Technical Papers (2000) pp. 120-121” (Non-Patent Document 2)), and the other is a MONOS (Metal Oxide Nitride Oxide Semiconductor) method in which charges are accumulated in an insulating film such as a silicon nitride film having a property to store charges (e.g., Patent Document 1 and Non-Patent Document 1).
In both of the two types of charge-holding methods, a silicon oxide film having excellent insulation properties is inserted between a region to accumulate charges and a silicon substrate. However, in the floating-gate method, when leakage paths locally occur in the silicon oxide film, held charges leak toward the substrate side through these leakage paths, which poses a problem that the held charges cannot be maintained. On the other hand, in the MONOS method, since held charges are spatially discretized in the insulating film functioning as a charge-holding film, only the held charges in the periphery of leakage paths leak. Therefore, it has an advantage that extreme reduction in charge-holding life does not occur.
FIG. 28 shows the split-gate memory cell utilizing self-alignment technique, that is, a cross-sectional structure of a memory cell that adopts the MONOS method as its charge-holding method. The memory cell is comprised of a select MOS transistor and a memory MOS transistor. After a select gate 32 is formed, a memory gate 31 is formed on a sidewall of the select gate 32 in a self-alignment manner with interposing a gate insulating film 33 therebetween. A gate insulating film 34 of the select MOS transistor is comprised of a silicon oxide film. The gate insulating film 33 of the memory MOS transistor is comprised of a three-layered film of a bottom oxide film 33a as a first potential barrier film, a silicon nitride film 33b as a charge-holding film, and a top oxide film 33c as a second potential barrier film stacked in this order. Although not shown, the select gate 32 is connected to a select gate line, and the memory gate 31 is connected to a word line, respectively. Further, a source region 35 of the select MOS transistor is connected to a common source line, and a drain region 36 of the memory MOS transistor is connected to a data line, respectively.
In the writing to the memory cell, a predetermined voltage is applied to the drain region 36 and the memory gate 31 of the memory MOS transistor simultaneously with turning the select MOS transistor to an ON state. At this time, by setting the condition that a high electric field is generated in a boundary region between the select MOS transistor and memory MOS transistor, hot electrons occur on a surface of the silicon substrate 30 in this region and then part of them are injected to the memory gate 31 side (SSI: Source Side Injection). These injected hot electrons are trapped in the silicon nitride film 33b which is a part of the gate insulating film 33 of the memory MOS transistor, and the information is thus written. On the other hand, in the deletion of the information, a negative bias is applied to the memory gate 31 and a positive bias is applied to the drain region 36 to generate hot holes by interband tunneling injection, and the hot holes are injected into the silicon nitride film 33b to neutralize electrons (hot-hole erasing).
Further, in order to improve efficiency of the writing operation described above, a structure is known, in which a lower surface of the silicon nitride film 33b as the charge-holding film is located lower than an interface between the gate insulating film 34 of the select MOS transistor and the silicon substrate 1 as shown in FIG. 29 (e.g., Japanese Patent Application Laid-Open Publication No. 2004-186663 (Patent Document 3) and Japanese Patent Application Laid-Open Publication No. 2001-168219 (Patent Document 4)).